The present invention relates to semiconductors, and more specifically, to a method for dummy gate formation using a spacer pull down hardmask.
A metal-oxide-semiconductor field-effect transistor (MOSFET) is a transistor used for amplifying or switching electronic signals. The MOSFET has a source, a drain, and a metal oxide gate electrode. The metal gate is electrically insulated from the main semiconductor n-channel or p-channel by a thin layer of insulating material, for example, silicon dioxide or glass, which makes the input resistance of the MOSFET relatively high. The gate voltage controls whether the path from drain to source is an open circuit (“off”) or a resistive path (“on”). A fin type field effect transistor (FET) is a type of MOSFET. FinFET devices include an arrangement of fins disposed on a substrate. The fins are formed from a semiconductor material. A gate stack is arranged over the fins and defines a channel region of the fins, while regions of the fins extending outwardly from the channel region define active source and drain regions of the device. Various state-of-the-art techniques may be used for forming the fin.
The gate stack may be formed by first forming a dummy gate stack. A dummy gate stack may be formed by depositing a conformal dummy gate material over a hardmask layer, the fins, and a substrate. The dummy gate material is patterned using a lithographic etching process to define a dummy gate stack by removing portions of the dummy gate material to expose source and drain regions of the fins.